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Experiment 8
Enabled AND Logic
Purpose: The purpose is to demonstrate AND logic in which charge is stored in
capacitance and accumulates to trigger the next segments. One input fails; two
inputs even at differing times will trigger an output.
The following code was used.
.tran 1 m 100 m uic
itrig1 0 1 dc ¼ 0 pwl(0,0,10us,5n,.2ms,5n,.21 ms,0)
itrig21 0 21 dc ¼ 0 pwl(0,0,5ms,0,5.010 ms,5n,5.2ms,
5n,5.21 ms,0)
x1 1 2 seg1
x2 2 3 seg1
x3 3 4 seg1
x4 4 5 seg1
x21 21 22 seg1
x22 22 23 seg1
x23 23 24 seg1
x24 24 5 seg1
c1 5 0 100pf ic ¼70mv
x5 5 6 seg1
x6 6 7 seg1
x7 7 8 seg1
x8 8 9 seg1
x9 9 10 seg1
x10 10 11 seg1
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