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Fig. 7.3 Symbol for
unconditional toggle or UT
Fig. 7.4 Symbol for single
controlled toggle, or SCT
according to the instructions in a wiring diagram, so in a sense the wiring diagram is
the program.
One usually visualizes registers to be horizontal; the flow of register operations
is usually imagined as going from left to right. A wiring diagram maintains this
concept.
Shown in the figure are the symbols for UT, SCT, and double controlled toggle
(DCT); these and other symbols, such as MCT, have been referred to as “gates.”
The term “gate” is misleading, as mentioned above, given that they are actually
toggles of various types. Figure 7.3 illustrates an unconditional toggle:
This applies to a simulated qubit which is in a true or a false state i such that a
logic value i L ¼
i 0 meaning the NOT of i.
This means that upon triggering, or application of a UT, a toggle occurs that is not
controlled by other signals, that is, an unconditional toggle. The wire is really a sort
of timeline from left to right, denoting before a trigger (on the left), and after a
trigger (on the right).
CMOS, for instance, might work from left to right but does not work backwards.
What differs from conventional logic is that a timeline of a wiring diagram may go
from right to left so that time, in a logical sense, can be reversed if need be. If i 0 is
applied on the right, then i appears on the left; this gate is logically reversible.
Reversibility has implications for data recovery and for reducing wasted energy
(calories). The bubble in a wiring diagram is the symbol for the unconditional toggle.
Figure 7.4 illustrates a single controlled NOT, or SCN:
There are two toggle switches involved, each in true or false states i and j. In this
case the input i L ¼
i on the left appears on the right as i R ¼
i on the left is simply carried through with no change so that on
the right i R ¼
i. The little black dot is a standard symbol indicating a connection,
meaning that toggle i controls toggle j. The j L ¼
j on the left is complemented only
if i is true. Another way of expressing what is accomplished by an SCN is
j R ¼
i
j
:
The symbol
means XOR of i with j, that is, XOR(i, j). If i is false, then j R ¼
j,
NOT(j), that is, j 0 . Inputs can be applied
to the right as readily as to the left, so the SCN is logically reversible. Note that the
input i is carried through unchanged and assures that information is not lost (as it
would be in irreversible logic).
and nothing happens. If i is true, then j R ¼
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