Plans for a Recall Referee - Brain Theory from a Circuits and Systems Perspective - page 111

Code Transfer
6. Refer to Fig. 6.5 . Redesign this circuit so that it uses a single many-input OR
gate instead of a chain of two-input OR gates.
Priority Selection
7. Refer to Fig. 6.8 . Redesign this circuit so that it uses only two-input OR gates
instead of one large many-input OR gate.
8. Apply the following numbers to the Fig. 6.9 four-priority comparator and
determine which gates pass a signal to the output. Mention as required U1, 2,
3, 4, 5, 6, 7, 8, 9.
(a) a, b, d, e are 011, 100, 010, 101
(b) Repeat for 101, 010, 111, 111
9. Refer to Fig. 6.10 . Use a truth table showing all internal variables, that is, each of
the outputs of units U1-U6 as the inputs a 3 b 3 count up in binary; trace the logic
possibilities and to prove that this comparator works to compare two bits as
advertised.
Enable Calculation Signal
10. Explain with a timing diagram how the logic works in Fig. 6.11 to generate an
Enable Calculations signal.