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Fig. 6.4 Structure of toggle registers for computations
This is an example of wired logic, similar to that of hardware buses using open
drain or open collector transistors.
A programmed toggle register may compute a wide variety of mathematical
functions. Here it will be arranged to sum the weights associated with attribute
encoding, the details of which are left to another chapter. An advantage of this
method is that several images in several register are going to compute priorities in
parallel.
Read Only Memory System
Running the codes that control the toggle registers is straightforward. They reside in
a special section of long-term memory, if not a special molecular memory packet.
Assuming long-term memory, the code at the top of a code stack is applied first,
then the next, and so on until the end of the program. A counter and decoder are not
required if the codes are fed periodically to the toggle registers at a proper rate.
Figure 6.5 shows how this might be accomplished.
Code 1, carried by a neural bus of L paths, is applied first through U1. Then, after
a delay, code 1 is disconnected and code 2 is applied through U2. This ripple
process is repeated until the end, code Z. The various OR gates serve to transmit the
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