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Fig. 5.7 Shift register left-to-right shift register using toggle elements
Shift Register
A shift register forms the basis of a pseudorandom number generator to be
described below. This style of generator is well suited to systems that operate
without a central clock. However there must be a local sequence of pulses to
cause data to shift through the resulting register. Figure 5.7 illustrates a plan.
The D i are a stream of 0s and 1s that are going to be “clocked” into the register.
A sequence of pulse bursts serving as a clock are coordinated with the D i . The clock
may be little more than a signal to modify the cues. This signal is converted into an
accurate clock pulse via synapse S1.
The shift register works as follows. If D i is true while Q 0 is false, for instance,
then XOR unit 1 applies a true to the AND gate U2. A clock pulse subsequently
causes Tog1 to toggle so that Q 0 goes to 1. But if D i is true while Q 0 is also true,
then XOR unit 1 applies a false to the AND gate U2 and no further toggle occurs.
Essentially the value of D i is moved into Q 0 .
This also works to shift in a D i of false. If Q 0 is 0 there is no toggle; if Q 0 is 1 it is
toggled to zero. Again the value of D i is moved into Q 0 , giving a shift operation.
Similar shift register elements may be cascaded to produce a code of any number of
bits. In the field of computer science a binary code is usually shifted into a register
in order to store it temporarily. The goal of a pseudorandom number generator is not
to store, but to constantly change numbers in a way that appears random.
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