Outline of a Cue Editor - Brain Theory from a Circuits and Systems Perspective - page 83

A reader must keep in mind that a cue editor does not judge relevance of cues,
this being the purpose of a recall referee to be described in subsequent chapters.

Brain System Environment

There is no fixed schematic of a cue editor, just like there is no fixed schematic for a
brain as far as we know; probably each brain differs. But there seems to be a general
plan which may be implemented in various ways. The electrical and logical designs
offered below demonstrate a particular implementation plan for a cue editor.
When modeling neural circuits, a full assortment of dendritic logic and enabled
(soma) logic are available. Also available are regular synapses to excite pulse
bursts, and weak synapses with an ability to excite a single pulse for precise timing.
Also of interest are specialized STM neurons to provide bursts of specified lengths.
All of the above circuit elements are involved, although in the interests of readabil-
ity and in keeping with the spirit of an overview, generic logic symbols are used as
much as possible. For similar reasons timing diagrams and requirements are not
emphasized below, even though such considerations are important in a practical
implementation.

Cue Editor Overview

Cues are assumed to be provided by images imposed by the body senses, and also
images from long-term memory. When a new image appears in conscious STM, its
attributes linger for a while, usually a brief while until updated. During this brief
duration cues taken from attributes are available for memory searches.

Proposed Architecture

Figure 5.1 suggests a possible architecture for a cue editor. There is a neural bus
with K axons to carry a maximum of K cues. The bus symbol /K means a bus with K
conductive paths. There is a control line labeled New(i), where i D; “i”

is an index mainly for explanatory purposes. New(1) goes true (emits a signal) to
signal a new set of cues, perhaps from the first image after awakening. Then comes
New(2) and so on throughout the day.
The logic will be such that immediately after New(1) goes true, there is a search
of long-term memory for an association with the given cues. Most often there is a
match, or a Hit, after which the system waits for New(2), and the next set of cues.
But if no exact matches are found, a NoHit signal is emitted from long-term
memory. In this event cues are loaded into a register R1 assumed cleared and ready

¼ 1, 2, 3,

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