Digital Signal Processing Reference
In-Depth Information
Digital Realisation
Counter
up/
down
+
Digital
Transmission
+
-
1 Bit ADC
DAC
Delta-modulator
Delta-demodulator
Counter
up/
down
DAC
Difference signal
DAC signal at the
output
Delta-modulated signal
Illustration 227:
Realisation of the
Δ
-encoder and signal curve in the case of higher sampling rate
In this representation of the digital schematic block diagram it can be clearly seen where analog
technology is still used: at the transmitter input, the receiver output and - this always applies - on the
transmission route. The time and value discrete digital integrator is realised by means of a forward-back-
ward counter followed by a DAC (digital analog converter).
Note for the following Illustration the technical identity of the negative feedback branch and the receiver
circuit. Both are
modulators. The reference signal fed into the difference modul
corresponds exactly to the time and value discrete (here sinusoidal) input signal recoved in the receiver.
The difference between the two, i.e. the difference signal is equivalent to “quantisation noise”.
Δ−
encoders or
Δ−
In the signal curve shown at the bottom a higher sampling rate was selected. The
-encoding can be
clearly seen. The maximum and minimum values of the deltamodulated signal lie where the upward or
downward gradient are greatest. The floating averaging would reproduce the gradient curve of the origi-
nal signal, i.e. the differentiated input signal.
Δ
The
encoded signal at the bottom is roughly equivalent to a pulse length modulated signal (see
Illustration 187). Unlike the continuous time pulse length modulated signal there here we have a kind of
pulse length modulated time discrete signal.
Δ−
