Image Processing Reference
In-Depth Information
to aid understanding of the techniques as well as provide a clue to implementation.
The circuits are largely canonical and so are not necessarily the most efficient
means of implementation. In practice, hardware optimization and implementation
software will reduce the circuits to their minimum form, those requiring a direct
route to extremely efficient hardware should see the work of Gasteros who has spe-
cialized heavily in this area.
6 9
Other examples of hardware implementation of non-
linear filters are given in the reference section.
10 15
The general framework for implementing all types of filters presented in this
topic and based on computational morphology is shown in Fig. 8.3. This frame-
work was described in more general terms in the previous chapter and is placed in
the context of hardware here to reinforce the concepts.
The structure presented assumes that the image data is stored as unsigned inte-
gers in binary format. The example shows 3-bit data forming a stack of eight
threshold levels.
Consistent with computational morphology, the circuit contains three sec-
tions:
1.
stacking,
2.
filtering, and
3.
unstacking.
The
stacking
section converts the
n
binary digits
I
0
,
I
2
,…
I
n
1
of a number
N
, to its
L
threshold levels
x
0
,
x
2
,…
x
L
1
, where
x
i
=
1
x
i
= 0
for
0 <
i
≤
N
and
for
N
<
i
≤
L
- 1,
(8.2)
andL=2
n
.
This is produced by a straightforward piece of digital logic design.
16
An exam-
ple for
n
=3,
L
= 8 is given in Fig. 8.4. The truth table mapping is given in
Fig. 8.4(a). This means that eight functions
x
i
, for each threshold level
i
need to be
Figure 8.3
General structure of hardware for nonlinear grayscale processing.
