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binary to the multiclass case. This is succeeded by Sect. 5.3 which investigates under
the light of SLT how the implementation of this new model brings advantages with
respect to the generalization ability of the algorithm. Experiments shown in Sect. 5.4
comparative results between this approach and the traditional SVM in terms of recog-
nition performance, speed and battery consumption. Finally the chapter is fully sum-
marized in Sect. 5.5 .
5.2 The Hardware-Friendly Multiclass SVM
Here we introduce the MC-HF-SVM approach which consists of a reformulation of
the SVM minimization problem in order to learn a model that allows the prediction
of activity samples using only fixed-point notation. Although the learning process is
itself performed with floating-point operations, its resulting model parameters and
the FFP are not. Thereby, this approach makes possible a fully fixed-point implemen-
tation of prediction modules in hardware devices. MC-HF-SVM allows to vary the
fixed-point number representation in terms of number of bits ( k ) to control over model
accuracy and complexity, leading to noticeable improvements in terms of recognition
speed and battery energy sparing without influencing recognition accuracy.
Figure 5.1 depicts schematically the basic HAR process including its main com-
ponents: Data collection, signal processing, feature extraction and classification. In
this section we focus only in the classification part, first by introducing the binary
problemand then by generalizing the hardware-friendly approach tomultiple classes.
5.2.1 The Binary Hardware-Friendly Formulation
The dual formulation of the original SVM (Eq. ( 2.13 ) ) is evidently invalid for its use
in fixed-point arithmetic because the
ʱ i values belong to the group of real numbers
limited between 0 and C . To overcome this issue, a normalization process can be
employed. This process maintains the SVM accuracy unchanged because it does not
Feature
Selection
Classification
Fig. 5.1 Activity recognition process pipeline
 
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