Hardware Reference
In-Depth Information
processor to keep the instruction pipeline full while running at a high rate of speed. A special
fetch/decode unit in the processor uses a highly optimized branch-prediction algorithm to predict the
direction and outcome of the instructions being executed through multiple levels of branches, calls,
and returns. It is similar to a chess player working out multiple strategies in advance of game play by
predicting the opponent's strategy several moves into the future. By predicting the instruction outcome
in advance, the instructions can be executed with no waiting.
Dataflow Analysis
Dataflow analysis
studies the flow of data through the processor to detect any opportunities for out-
of-order instruction execution. A special dispatch/execute unit in the processor monitors many
instructions and can execute these instructions in an order that optimizes the use of the multiple
superscalar execution units. The resulting out-of-order execution of instructions can keep the
execution units busy even when cache misses and other data-dependent instructions might otherwise
hold things up.
Speculative Execution
Speculative execution
is the processor's capability to execute instructions in advance of the actual
program counter. The processor's dispatch/execute unit uses dataflow analysis to execute all
available instructions in the instruction pool and store the results in temporary registers. A retirement
unit then searches the instruction pool for completed instructions that are no longer data dependent on
other instructions to run or which have unresolved branch predictions. If any such completed
instructions are found, the retirement unit or the appropriate standard Intel architecture commits the
results to memory in the order they were originally issued. They are then retired from the pool.
Dynamic execution essentially removes the constraint and dependency on linear instruction
sequencing. By promoting out-of-order instruction execution, it can keep the instruction units working
rather than waiting for data from memory. Even though instructions can be predicted and executed out
of order, the results are committed in the original order so they don't disrupt or change program flow.
This enables the P6 to run existing Intel architecture software exactly as the P5 (Pentium) and
previous processors did—just a whole lot more quickly!
Dual Independent Bus Architecture
The Dual Independent Bus (DIB) architecture was first implemented in the sixth-generation
processors from Intel and AMD. DIB was created to improve processor bus bandwidth and
performance. Having two (dual) independent data I/O buses enables the processor to access data
from either of its buses simultaneously and in parallel, rather than in a singular sequential manner (as
in a single-bus system). The main (often called
front-side
) processor bus is the interface between the
processor and the motherboard or chipset. The second (back-side) bus in a processor with DIB is
used for the L2 cache, enabling it to run at much greater speeds than if it were to share the main
processor bus.
Two buses make up the DIB architecture: the L2 cache bus and the main CPU bus, often called
FSB
(front side bus)
. The P6 class processors, from the Pentium Pro to the Core 2, as well as Athlon 64
processors can use both buses simultaneously, eliminating a bottleneck there. The dual bus
architecture enables the L2 cache of the newer processors to run at full speed inside the processor
core on an independent bus, leaving the main CPU bus (FSB) to handle normal data flowing in and
out of the chip. The two buses run at different speeds. The front-side bus or main CPU bus is coupled
