Hardware Reference
In-Depth Information
reducing or hiding memory delays by exploiting the overlap of processor operations with data
accesses. A nonblocking cache enables program execution to proceed concurrently with cache misses
as long as certain dependency constraints are observed. In other words, the cache can handle a cache
miss much better and enable the processor to continue doing something nondependent on the missing
data.
The cache controller built into the processor also is responsible for watching the memory bus when
alternative processors, known as
bus masters
, control the system. This process of watching the bus is
referred to as
bus snooping
. If a bus master device writes to an area of memory that also is stored in
the processor cache currently, the cache contents and memory no longer agree. The cache controller
then marks this data as invalid and reloads the cache during the next memory access, preserving the
integrity of the system.
All PC processor designs that support cache memory include a feature known as a
translation
lookaside buffer
(TLB) to improve recovery from cache misses. The TLB is a table inside the
processor that stores information about the location of recently accessed memory addresses. The TLB
speeds up the translation of virtual addresses to physical memory addresses.
As clock speeds increase, cycle time decreases. Newer systems no longer use cache on the
motherboard because the faster system memory used in modern systems can keep up with the
motherboard speed. Modern processors integrate the L2 cache into the processor die just like the L1
cache, and most recent models include on-die L3 as well. This enables the L2/L3 to run at full-core
speed because it is now part of the core.
Processor Features
As new processors are introduced, new features are continually added to their architectures to
improve everything from performance in specific types of applications to the reliability of the CPU as
a whole. The next few sections look at some of these technologies.
System Management Mode (SMM)
Spurred on initially by the need for more robust power management capabilities in mobile computers,
Intel and AMD began adding
System Management Mode
(SMM) to its processors during the early
1990s. SMM is a special-purpose operating mode provided for handling low-level system power
management and hardware control functions. SMM offers an isolated software environment that is
transparent to the OS or applications software and is intended for use by system BIOS or low-level
driver code.
SMM was introduced as part of the Intel 386SL mobile processor in October 1990. SMM later
appeared as part of the 486SL processor in November 1992, and in the entire 486 line starting in June
1993. SMM was notably absent from the first Pentium processors when they were released in March
1993; however, SMM was included in all 75MHz and faster Pentium processors released on or after
October 1994. AMD added SMM to its enhanced Am486 and K5 processors around that time as
well. All other Intel and AMD x86-based processors introduced since that time also have
incorporated SMM.
SMM is invoked by signaling a special interrupt pin on the processor, which generates a System
Management Interrupt (SMI), the highest priority nonmaskable interrupt available. When SMM starts,
the context or state of the processor and currently running programs are saved. Then the processor
switches to a separate dedicated address space and executes the SMM code, which runs transparently
