Hardware Reference
In-Depth Information
is there, it can be read from the faster cache; if it isn't, it has to be read from the much slower main
memory.
Various ways of organizing or mapping the tags affect how cache works. A cache can be mapped as
fully associative, direct-mapped, or set associative.
In a
fully associative mapped cache
, when a request is made for data from a specific main memory
address, the address is compared against all the address tag entries in the cache tag RAM. If the
requested main memory address is found in the tag (a
hit
), the corresponding location in the cache is
returned. If the requested address is not found in the address tag entries, a
miss
occurs, and the data
must be retrieved from the main memory address instead of the cache.
In a
direct-mapped cache
, specific main memory addresses are preassigned to specific line locations
in the cache where they will be stored. Therefore, the tag RAM can use fewer bits because when you
know which main memory address you want, only one address tag needs to be checked, and each tag
needs to store only the possible addresses a given line can contain. This also results in faster
operation because only one tag address needs to be checked for a given memory address.
A
set associative cache
is a modified direct-mapped cache. A direct-mapped cache has only one set
of memory associations, meaning a given memory address can be mapped into (or associated with)
only a specific given cache line location. A two-way set associative cache has two sets, so that a
given memory location can be in one of two locations. A four-way set associative cache can store a
given memory address into four different cache line locations (or sets). By increasing the set
associativity, the chance of finding a value increases; however, it takes a little longer because more
tag addresses must be checked when searching for a specific location in the cache. In essence, each
set in an
n
-way set associative cache is a subcache that has associations with each main memory
address. As the number of subcaches or sets increases, eventually the cache becomes fully
associative—a situation in which any memory address can be stored in any cache line location. In that
case, an
n
-way set associative cache is a compromise between a fully associative cache and a direct-
mapped cache.
In general, a direct-mapped cache is the fastest at locating and retrieving data from the cache because
it has to look at only one specific tag address for a given memory address. However, it also results in
more misses overall than the other designs. A fully associative cache offers the highest hit ratio but is
the slowest at locating and retrieving the data because it has many more address tags to check through.
An
n
-way set associative cache is a compromise between optimizing cache speed and hit ratio, but
the more associativity there is, the more hardware (tag bits, comparator circuits, and so on) is
required, making the cache more expensive. Obviously, cache design is a series of trade-offs, and
what works best in one instance might not work best in another. Multitasking environments such as
Windows are good examples of environments in which the processor needs to operate on different
areas of memory simultaneously and in which an
n
-way cache can improve performance.
The contents of the cache must always be in sync with the contents of main memory to ensure that the
processor is working with current data. For this reason, the internal cache in the 486 family was a
write-through
cache. Write-through means that when the processor writes information to the cache,
that information is automatically written through to main memory as well.
By comparison, Pentium and later chips have an internal write-back cache, which means that both
reads and writes are cached, further improving performance.
Another feature of improved cache designs is that they are
nonblocking
. This is a technique for
