Hardware Reference
In-Depth Information
Figure 1.2. Cutaway view of an NMOS transistor.
A PMOS transistor works in a similar but opposite fashion. P-type silicon is used for the source and
drain, with N-type silicon positioned between them. When a negative voltage is placed on the gate,
the gate electrode creates a field that repels electrons from the N-type silicon between the source and
drain. That in turn changes that area to behave as if it were P-type silicon, creating a path for current
to flow and turning the transistor “on.”
When both NMOS and PMOS field-effect transistors are combined in a complementary arrangement,
power is used only when the transistors are switching, making dense, low-power circuit designs
possible. Because of this, virtually all modern processors are designed using CMOS (Complementary
Metal Oxide Semiconductor) technology.
Compared to a tube, a transistor is much more efficient as a switch and can be miniaturized to
microscopic scale. Since the transistor was invented, engineers have strived to make it smaller and
smaller. In 2003, NEC researchers unveiled a silicon transistor only 5 nanometers (billionths of a
meter) in size. Other technologies, such as Graphene and carbon nanotubes, are being explored to
produce even smaller transistors, down to the molecular or even atomic scale. In 2008, British
researchers unveiled a Graphene-based transistor only 1 atom thick and 10 atoms (1nm) across, and
in 2010, IBM researchers created Graphene transistors switching at a rate of 100 gigahertz, thus
paving the way for future chips denser and faster than possible with silicon-based designs.
In 2012, Intel introduced its Ivy Bridge processors using a revolutionary new Tri-Gate three-
dimensional transistor design, manufactured using a 22nm process. This design was first announced
by Intel back in 2002; however, it took 10 years to complete the development and to create the
manufacturing processes for production. Tri-Gate transistors differ from conventional two-
dimensional planar transistors in that the source is constructed as a raised “fin,” with three conducting
channels between the source and the drain (see
Figure 1.3
). This allows much more surface area for
conduction than the single flat channel on a planar transistor and improves the total drive current and
switching speed with less current leakage. Intel states that this technology also allows for lower
voltages, resulting in up to a 50% reduction in power consumption while maintaining or even
