Hardware Reference
In-Depth Information
typically lack support for either parity or ECC.
How Parity Checking Works
IBM originally established the odd parity standard for error checking. The following explanation
might help you understand what is meant by odd parity. As the 8 individual bits in a byte are stored in
memory, a parity generator/checker, which is either part of the CPU or located in a special chip on
the motherboard, evaluates the data bits by adding up the number of 1s in the byte. If an even number
of 1s is found, the parity generator/checker creates a 1 and stores it as the ninth bit (parity bit) in the
parity memory chip. That makes the sum for all 9 bits (including the parity bit) an odd number. If the
original sum of the 8 data bits is an odd number, the parity bit created would be a 0, keeping the sum
for all 9 bits an odd number. The basic rule is that the value of the parity bit is always chosen so that
the sum of all 9 bits (8 data bits plus 1 parity bit) is stored as an odd number. If the system used even
parity, the example would be the same except the parity bit would be created to ensure an even sum. It
doesn't matter whether even or odd parity is used; the system uses one or the other, and it is
completely transparent to the memory chips involved. Remember that the 8 data bits in a byte are
numbered 0 1 2 3 4 5 6 7. The following examples might make it easier to understand:
Data bit number: 0 1 2 3 4 5 6 7 Parity bit
Data bit value: 1 0 1 1 0 0 1 1 0
In this example, because the total number of data bits with a value of 1 is an odd number (5), the
parity bit must have a value of 0 to ensure an odd sum for all 9 bits.
Here is another example:
Data bit number: 0 1 2 3 4 5 6 7 Parity bit
Data bit value: 1 1 1 1 0 0 1 1 1
In this example, because the total number of data bits with a value of 1 is an even number (6), the
parity bit must have a value of 1 to create an odd sum for all 9 bits.
When the system reads memory back from storage, it checks the parity information. If a (9-bit) byte
has an even number of bits, that byte must have an error. The system can't tell which bit has changed
or whether only a single bit has changed. If 3 bits changed, for example, the byte still flags a parity-
check error; if 2 bits changed, however, the bad byte could pass unnoticed. Because multiple bit
errors (in a single byte) are rare, this scheme gives you a reasonable and inexpensive ongoing
indication that memory is good or bad.
ECC
ECC goes a big step beyond simple parity-error detection. Instead of just detecting an error, ECC
allows a single bit error to be corrected, which means the system can continue without interruption
and without corrupting data. ECC, as implemented in most PCs, can only detect, not correct, double-
bit errors. Because studies have indicated that approximately 98% of memory errors are the single-bit
variety, the most commonly used type of ECC is one in which the attendant memory controller detects
and corrects single-bit errors in an accessed data word. (Double-bit errors can be detected but not
corrected.) This type of ECC is known as
single-bit error-correction double-bit error detection
(SEC-DED) and requires an additional 7 check bits over 32 bits in a 4-byte system and an additional
