Hardware Reference
In-Depth Information
DRAM memory that supports paging and this bursting technique is called
Fast Page Mode
(FPM)
memory. This term refers to the ability to access data on the same memory page faster than data on
other memory pages.
Most 386, 486, and Pentium systems from 1987 through 1995 used FPM memory, which came in
either 30-pin or 72-pin SIMM form.
Another technique for speeding up FPM memory is called
interleaving
. In this design, two separate
banks of memory are used together, alternating access from one to the other as even and odd bytes.
While one is being accessed, the other is being precharged, when the row and column addresses are
being selected. Then, by the time the first bank in the pair is finished returning data, the second bank
in the pair is finished with the latency part of the cycle and is now ready to return data. While the
second bank is returning data, the first bank is being precharged, selecting the row and column
address of the next access. This overlapping of accesses in two banks reduces the effect of the latency
or precharge cycles and allows for faster overall data retrieval. The only problem is that to use
interleaving, you must install identical pairs of banks together, doubling the number of modules
required.
Extended Data Out RAM
In 1995, a newer type of DRAM called extended data out (EDO) RAM became available for Pentium
systems. EDO, a modified form of FPM memory, is sometimes referred to as Hyper Page mode. EDO
was invented and patented by Micron Technology, although Micron licensed production to many other
memory manufacturers.
EDO memory consists of specially manufactured chips that allow a timing overlap between
successive accesses. The name
extended data out
refers specifically to the fact that, unlike FPM, the
data output drivers on the chip are not turned off when the memory controller removes the column
address to begin the next cycle. This enables the next cycle to overlap the previous one, saving
approximately 10ns per cycle.
The effect of EDO is that cycle times are improved by enabling the memory controller to begin a new
column address instruction while it is reading data at the current address. This is almost identical to
what was achieved in older systems by interleaving banks of memory, but unlike interleaving, with
EDO you didn't need to install two identical banks of memory in the system at a time.
EDO RAM allows for burst mode cycling of 5-2-2-2, compared to the 5-3-3-3 of standard fast page
mode memory. To do four memory transfers, then, EDO would require 11 total system cycles,
compared to 14 total cycles for FPM. This is a 22% improvement in overall cycling time. The
resulting two-cycle (30ns) cycle time during burst transfers equals a 33.3MHz effective clock rate,
compared to 45ns/22MHz for FPM. On a system with a 64-bit (8-byte) wide memory bus, this would
result in a maximum throughput of 266MBps (33.3MHz × 8 bytes = 266MBps). Due to the processor
cache, EDO typically increased overall system benchmark speed by only 5% or less. Even though the
overall system improvement was small, the important thing about EDO was that it used the same
basic DRAM chip design as FPM, meaning that there was practically no additional cost over FPM. In
fact, in its heyday EDO cost less than FPM yet offered higher performance.
EDO RAM generally came in 72-pin SIMM form.
Figure 6.4
(later in this chapter) shows the
physical characteristics of these SIMMs.
