Hardware Reference
In-Depth Information
Figure 6.3. CPU-Z screenshots showing the Memory/SPD information for a system with DDR3-
1600 SDRAM.
The following sections look at these memory types in more detail.
Fast Page Mode DRAM
Standard DRAM is accessed through a technique called
paging
. Normal memory access requires that
a row and column address be selected, which takes time. Paging enables faster access to all the data
within a given row of memory by keeping the row address the same and changing only the column.
Memory that uses this technique is called
Page Mode
or
Fast Page Mode memory
. Other variations
on Page Mode were called Static Column or Nibble Mode memory.
Paged memory is a simple scheme for improving memory performance that divides memory into
pages ranging from 512 bytes to a few kilobytes long. The paging circuitry then enables memory
locations in a page to be accessed with fewer wait states. If the desired memory location is outside
the current page, one or more wait states are added while the system selects the new page.
To improve further on memory access speeds, systems have evolved to enable faster access to
DRAM. One important change was the implementation of burst mode access in the 486 and later
processors. Burst mode cycling takes advantage of the consecutive nature of most memory accesses.
After setting up the row and column addresses for a given access, using burst mode, you can then
access the next three adjacent addresses with no additional latency or wait states. A burst access
usually is limited to four total accesses. To describe this, we often refer to the timing in the number of
cycles for each access. A typical burst mode access of standard DRAM is expressed as x-y-y-y; x is
the time for the first access (latency plus cycle time), and y represents the number of cycles required
for each consecutive access.
Standard 60ns-rated DRAM normally runs 5-3-3-3 burst mode timing. This means the first access
takes a total of five cycles (on a 66MHz system bus, this is about 75ns total, or 5 × 15ns cycles), and
the consecutive cycles take three cycles each (3 × 15ns = 45ns). As you can see, the actual system
timing is somewhat less than the memory is technically rated for. Without the bursting technique,
memory access would be 5-5-5-5 because the full latency is necessary for each memory transfer. The
45ns cycle time during burst transfers equals about a 22.2MHz effective clock rate; on a system with
a 64-bit (8-byte) wide memory bus, this would result in a maximum throughput of 177MBps
(22.2MHz × 8 bytes = 177MBps).
