Memory - Upgrading and Repairing PCs - page 316

which is much more cost effective. The SRAM cache runs at speeds close to or even equal to the
processor and is the memory from which the processor usually directly reads from and writes to.
During read operations, the data in the high-speed cache memory is resupplied from the lower-speed
main memory or DRAM in advance. To convert access time in nanoseconds to MHz, use the
following formula:
1 / nanoseconds × 1000 = MHz
Likewise, to convert from MHz to nanoseconds, use the following inverse formula:
1 / MHz × 1000 = nanoseconds
Today, we have memory that runs faster than 1GHz (1 nanosecond), but up until the late 1990s,
DRAM was limited to about 60ns (16MHz) in speed. Up until processors were running at speeds of
16MHz, the available DRAM could fully keep pace with the processor and motherboard, meaning
that there was no need for cache. However, as soon as processors crossed the 16MHz barrier, the
available DRAM could no longer keep pace, and SRAM cache began to enter PC system designs.
This occurred way back in 1986 and 1987 with the debut of systems with the 386 processor running
at speeds of 16MHz to 20MHz or faster. These were among the first PC systems to employ what's
called cache memory , a high-speed buffer made up of SRAM that directly feeds the processor.
Because the cache can run at the speed of the processor, it acts as a buffer between the processor and
the slower DRAM in the system. The cache controller anticipates the processor memory needs and
preloads the high-speed cache memory with data. Then, as the processor calls for a memory address,
the data can be retrieved from the high-speed cache rather than the much lower-speed main memory.
Cache effectiveness can be expressed by a hit ratio. This is the ratio of cache hits to total memory
accesses. A hit occurs when the data the processor needs has been preloaded into the cache from the
main memory, meaning the processor can read it from the cache. A cache miss is when the cache
controller did not anticipate the need for a specific address and the desired data was not preloaded
into the cache. In that case the processor must retrieve the data from the slower main memory, instead
of the faster cache. Any time the processor reads data from main memory, the processor must wait
longer because the main memory cycles at a much slower rate than the processor. As an example, if
the processor with integral on-die cache is running at 3.6GHz (3,600MHz) on a 1,333MHz bus, both
the processor and the integral cache would be cycling at 0.28ns, whereas the main memory would
most likely be cycling almost five times more slowly at 1,333MHz (0.75ns). So, every time the
3.6GHz processor reads from main memory, it would effectively slow down to only 1,333MHz. The
slowdown is accomplished by having the processor execute what are called wait states , which are
cycles in which nothing is done; the processor essentially cools its heels while waiting for the slower
main memory to return the desired data. Obviously, you don't want your processors slowing down, so
cache function and design become more important as system speeds increase.
To minimize the processor being forced to read data from the slow main memory, two or three stages
of cache usually exist in a modern system, called Level 1 (L1), Level 2 (L2), and Level 3 (L3). The
L1 cache is also called integral or internal cache because it has always been built directly into the
processor as part of the processor die (the raw chip). Because of this, L1 cache always runs at the
full speed of the processor core and is the fastest cache in any system. All 486 and higher processors
incorporate integral L1 cache, making them significantly faster than their predecessors. L2 cache was
originally called external cache because it was external to the processor chip when it first appeared.
Originally, this meant it was installed on the motherboard, as was the case with all 386, 486, and
first-generation Pentium systems. In those systems, the L2 cache runs at motherboard and CPU bus