Hardware Reference
In-Depth Information
concurrently, with each interrupt nesting within another.
The ISA bus uses edge-triggered interrupt sensing, in which an interrupt is sensed by a changing
signal sent on a particular wire located in the slot connector. A different wire corresponds to each
possible hardware interrupt. Because the motherboard can't recognize which slot contains the card
that used an interrupt line and therefore generated the interrupt, confusion results if more than one
card is set to use a particular interrupt. Each interrupt, therefore, is usually designated for a single
hardware device. Most of the time, interrupts can't be shared.
Originally, IBM developed ways to share interrupts on the ISA bus, but few devices followed the
necessary rules to make this a reality. The PCI bus inherently allows interrupt sharing; in fact,
virtually all PCI cards are set to PCI interrupt A and share that interrupt on the PCI bus. The real
problem is that there are technically two sets of hardware interrupts in the system: PCI interrupts and
ISA interrupts. For PCI cards to work in a PC, the PCI interrupts are first mapped to ISA interrupts,
which are then configured as nonshareable. Therefore, on older systems, you must assign a
nonconflicting interrupt for each card, even PCI cards. The conflict between assigning ISA IRQs for
PCI interrupts caused many configuration problems for early users of PCI motherboards and
continued to cause problems even after the development of Windows 95 and its PnP technology.
The solution to the interrupt sharing problem for PCI cards was something called PCI IRQ Steering ,
which has been supported in OSs (starting with Windows 95 OSR 2.x) and BIOSs for more than 15
years. PCI IRQ Steering allows a plug-and-play operating system such as Windows to dynamically
map or “steer” PCI cards (which almost all use PCI INTA#) to standard PC interrupts and allows
several PCI cards to be mapped to the same interrupt. More information on PCI IRQ Steering is found
in the section “ PCI Interrupts , ” later in this chapter.
Hardware interrupts are sometimes referred to as maskable interrupts , which means you can mask or
turn off the interrupts for a short time while the CPU is used for other critical operations. It is up to
the system BIOS and programs to manage interrupts properly and efficiently for the best system
performance.
The following sections discuss the IRQs that any standard devices use, as well as what might be free
in your system.
8-Bit ISA Bus Interrupts
The PC and XT (the systems based on the 8-bit 8086 CPU) provide for eight different external
hardware interrupts. Table 4.59 shows the typical uses for these interrupts, which are numbered 0-7.
Table 4.59. 8-Bit ISA Bus Default Interrupt Assignments
If you have a system that has one of the original 8-bit ISA buses, the IRQ resources that the system
 
 
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