Hardware Reference
In-Depth Information
Therefore, PCI cards do not have jumpers and switches and are instead configured through software.
True PnP systems are capable of automatically configuring the adapters, whereas non-PnP systems
with ISA slots must configure the adapters through a program that is usually a part of the system
CMOS configuration. Starting in late 1995, most PC-compatible systems have included a PnP BIOS
that allows the automatic PnP configuration.
PCI Express
During 2001, a group of companies called the Arapahoe Work Group (led primarily by Intel)
developed a draft of a new high-speed bus specification code-named 3GIO (third-generation I/O). In
August 2001, the PCI Special Interest Group (PCI-SIG) agreed to take over, manage, and promote the
3GIO architecture specification as the future generation of PCI. In April 2002, the 3GIO draft version
1.0 was completed, transferred to the PCI-SIG, and renamed PCI Express. Finally in July 2002, the
PCI Express 1.0 specification was approved. The specification was updated to 1.1 in April 2005, to
2.0 in January 2007, and to version 3.0 in November 2010. PCI Express 4.0 was announced in late
November 2011, but final specifications are not expected until sometime in either 2014 or 2015.
The original 3GIO code name was derived from the fact that this new bus specification was designed
to initially augment and eventually replace the previously existing ISA/AT-Bus (first-generation) and
PCI (second-generation) bus architectures in PCs. Each of the first two generations of PC bus
architectures was designed to have a 10-to-15-year useful life in PCs. In being adopted and approved
by the PCI-SIG, PCI Express is now destined to be the dominant PC bus architecture designed to
support the increasing bandwidth needs in PCs over the next 10-15 years.
The key features of PCI Express are as follows:
• Compatibility with existing PCI enumeration and software device drivers.
• Physical connection over copper, optical, or other physical media to allow for future encoding
schemes.
• Maximum bandwidth per pin allowing for small form factors, reduced cost, simpler board
designs and routing, and reduced signal integrity issues.
• Embedded clocking scheme that enables easy frequency (speed) changes compared to
synchronous clocking.
• Bandwidth (throughput) that increases easily with frequency and width (lane) increases.
• Low latency suitable for applications requiring isochronous (time-sensitive) data delivery, such
as streaming video.
• Hot-plugging and hot-swapping capabilities.
• Power management capabilities.
PCI Express is another example of how the PC has moved from parallel to serial interfaces. Earlier
generation bus architectures in the PC have been of a parallel design, in which multiple bits are sent
simultaneously over several pins in parallel. The more bits sent at a time, the faster the bus throughput
is. The timing of all the parallel signals must be the same, which becomes more and more difficult to
do over faster and longer connections. Even though 32 bits can be transmitted simultaneously over a
bus such as PCI or AGP, propagation delays and other problems cause them to arrive slightly skewed
at the other end, resulting in a time difference between when the first and last of all the bits arrive.
A serial bus design is much simpler, sending 1 bit at a time over a single wire, at much higher rates of
speed than a parallel bus would allow. By sending the bits serially, the timing of individual bits or
