Hardware Reference
In-Depth Information
This hub interface design allows for a much greater throughput for PCI devices because there is no
South Bridge chip (also carrying traffic from the Super I/O chip) hogging the PCI bus. Due to
bypassing PCI, the hub interface also enables greater throughput for devices directly connected to the
I/O controller hub (formerly the South Bridge), such as the higher-speed ATA-100/133, Serial ATA
3Gbps, and USB interfaces.
There are two main variations on the hub interface:
•
AHA (Accelerated Hub Architecture)
—Used by the 8xx series of chipsets. AHA is a 4X
(quad-clocked) 66MHz 8-bit (4 × 66MHz × 1 byte = 266MBps) interface, which has twice the
throughput of PCI (33MHz × 32 bits = 133MBps).
•
DMI (Direct Media Interface)
—Used by the 9xx and later series chipsets. DMI is basically a
dedicated four-lane (4-bit-wide) PCI Express connection allowing for 1GBps (250GHz × 4
bits) in each direction simultaneously, which is 7.5 to 14 times faster than PCI. DMI 2.0 was
introduced in 2011, and runs at 2GBps in each direction simultaneously.
These hub interface designs are also economical, being only 4 or 8 bits wide. Although this seems too
narrow to be useful, there is a reason for the design. The lower pin count for the AHA and DMI hub
connections means that less circuit routing exists on the board, less signal noise and jitter occur, and
the chips have many fewer pins, making them smaller and more economical to produce. So, by virtue
of a narrow—but fast—design, the hub interface achieves high performance with less cost and more
signal integrity than with the previous North/South Bridge design.
The ICH also includes a new LPC bus, consisting basically of a stripped 4-bit-wide version of PCI
designed primarily to support the motherboard ROM BIOS and Super I/O chips. Because the same
four signals for data, address, and command functions are used, only 9 other signals are necessary to
implement the bus, for a total of 13 signals. This dramatically reduces the number of traces connecting
the ROM BIOS chip and Super I/O chips in a system as compared to the 98 ISA bus signals necessary
for older North/South Bridge chipsets that used ISA as the interface to those devices. The LPC bus
has a maximum bandwidth of 16.67MBps, which is much faster than ISA and more than enough to
support devices such as ROM BIOS and Super I/O chips.
Figure 4.21
shows a typical Intel chipset-based motherboard that uses hub architecture.
