Hardware Reference
In-Depth Information
instructions into RISC86 instructions. These RISC86 instructions were designed specifically with
direct support for the x86 architecture while obeying RISC performance principles. They are simpler
and easier to execute than the complex x86 instructions. This type of capability is another feature
normally found only in P6 class processors.
The Nx586 was discontinued after the merger with AMD, which then took the design for the
successor Nx686 and released it as the AMD-K6.
AMD-K6 Series
The AMD-K6 processor is a high-performance sixth-generation processor that is physically
installable in a P5 (Pentium) motherboard. It essentially was designed for AMD by NexGen and was
first known as the Nx686. The NexGen version never appeared because AMD purchased it before the
chip was due to be released. The AMD-K6 delivers performance levels somewhere between the
Pentium and Pentium II processor because of its unique hybrid design.
The K6 processor contains an industry-standard, high-performance implementation of the new
multimedia instruction set, enabling a high level of multimedia performance for the period. The K6-2
introduced an upgrade to MMX that AMD calls 3DNow!, which adds even more graphics and sound
instructions. AMD designed the K6 processor to fit the low-cost, high-volume Socket 7 infrastructure.
Initially, it used AMD's 0.35-micron, five-metal layer process technology; later the 0.25-micron
process was used to increase production quantities because of reduced die size, as well as to
decrease power consumption.
AMD-K6 processor technical features include the following:
• Sixth-generation internal design, fifth-generation external interface
• Internal RISC core, which translates x86 to RISC instructions
• Superscalar parallel execution units (seven)
• Dynamic execution
• Branch prediction
• Speculative execution
• Large 64KB L1 cache (32KB instruction cache plus 32KB write-back dual-ported data cache)
• Built-in floating-point unit
• Industry-standard MMX instruction support
• System Management Mode
• Ceramic pin grid array (CPGA) Socket 7 design
• Manufactured using 0.35-micron and 0.25-micron, five-layer designs
The AMD-K6 processor architecture is fully x86 binary code compatible, which means it runs all
Intel software, including MMX instructions. To make up for the lower L2 cache performance of the
Socket 7 design, AMD beefed up the internal L1 cache to 64KB, twice the size of the Pentium II or
III. This, plus the dynamic execution capability, enabled the K6 to outperform the Pentium and come
close to the Pentium II and III in performance for a given clock rate.
There were two subsequent additions to the K6 family, in the form of the K6-2 and K6-3. The K6-2
offered higher clock and bus speeds (up to 100MHz) and support for the 3DNow! instruction set. The
K6-3 added 256KB of on-die full-core speed L2 cache. The addition of the full-speed L2 cache in the
