Digital Signal Processing Reference
In-Depth Information
This is called the bilinear interpolation technique. This is
exactly the same as the video scaling techniques discussed earlier.
As in video scaling, the complexity in the interpolation tech-
nique can be increased to 5
n
level. The disadvantage is the additional hardware resources that
are employed to implement this algorithm.
5, 6
6 or to any arbitrary n
8.2 A Simplistic HW Implementation of Bayer
Demosaicing
Since these algorithms have to be run at the pixel rate for HD
(high-definition) resolutions, the pixel rate is very high and so
FPGAs are used to implement custom demosaicing algorithms.
The logic inside the FPGA is structured as shown in
Figure 8.4
.
The Bayer data from the camera is fed into custom line buffers
built inside the FPGA. These line buffers are “n” wide, where “n”
is the horizontal resolution of the sensor (how many pixels per
line the sensor can provide).
The number of the line buffers that you need depends upon
your Bayer demosaicing algorithm. A bilinear implementation
may require just two line buffers, but a complex 5
5 interpola-
tion would need more line buffer resources.
Figure 8.4. Line buffer imple-
mentation for Bayer Demosaicing.
8.3 Sensor Processing in Military Electro-
optical Infrared Systems
Military imaging systems are becoming increasingly sophis-
ticated, incorporating multiple advanced sensors ranging from
thermal infrared to visible, and even to UV (ultraviolet) focal
planes. Not only do these sensor outputs need to be corrected,
interpolated and so forth, often images from multiple sensors
