Digital Signal Processing Reference
In-Depth Information
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COEFF
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MEMORY
MULTIPLIERS & ADDER
MEMORY
Figure 5.6.
multipliers. The outputs of the multipliers are then summed and
sent to a “Bit Narrower” which adjusts the size of the output to fit
into the number of bits allowed. The second stage has the same
basic structure as the first, and filters the “horizontal pixels”
output from the first stage to produce the final output pixel.
This structure can be extended to perform 5
9
multi-tap scaling. The principles remain the same, but larger
kernels will require more FPGA resources. As mentioned previ-
ously, each new pixel may use a different set of coefficients
depending on its location and will therefore require different
coefficient sets.
A programmable logic device with abundant hardware
resources, such as an FPGA, is a good platform on which to
implement a video scaling engine. In the implementation dis-
cussed, four multipliers are needed for scaling in the vertical
dimension (one for each column of the scaling kernel), four
multipliers are needed for scaling in the horizontal dimension
(one for each row of the kernel), and a significant amount of on-
chip memory is needed for video line buffers.
Generic DSP architectures, which typically have 1
5, 6
6, or 9
2 multiply-
and-accumulate (MAC) units and significantly lower memory
bandwidth, do not have the parallelism for such an imple-
mentation. However there are specialized DSPs that have
dedicated hardware to implement HD scaling in real-time.
There are various Intellectual Property (IP) providers for video
scaling functions in FPGAs. FPGA suppliers provide their own
functions as well, which considerably reduces the complexity of
implementing the function.
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