Digital Signal Processing Reference
In-Depth Information
time. The transfer of data will normally be controlled by “valid”,
with “ready” asserted occasionally to select the cycles on which
data is accepted.
The number of cycles on which “valid” is asserted depends on
the ratio between the screen resolution and the clock rate in the
flow-controlled domain. If the clock is just sufficient for the
highest resolution then “valid” will be asserted on most cycles
within the main part of the frame. At lower resolutions “valid” will
only be asserted on a proportion of the cycles.
The “ready” signal to the clocked video input should not be the
main source of flow control on the frame, so it is typically de-
asserted only for short periods to synchronise with the sink. One
common problem is that if “ready” is de-asserted for too long
then the memory buffer in the video input block can overflow.
Attaching a streaming video monitor to the output of the video
input block can help detect overflow situations
if the video
input block is backpressured (by de-asserting “ready”) for too
long then it will abandon the backpressured frame and send
a short packet. This can be seen on the trace.
The trace also reports the number of not-ready cycles within
each packet and the time interval between packets. This can be
used to check that the interface is being mostly flow-controlled by
“valid” rather than “ready”.
If the clocked video-input block has a control port then the
debug master can be used to check the overflow sticky-bit in the
status register. This bit will be set if there has been anoverflowsince
it was last checked - note that if you have software monitoring and
clearing this bit then reading it from the debugger will not be
reliable.
e
21.7 Converting from Flow-controlled to
Clocked Video Streams
The clocked-video output component converts flow-
controlled video packets into a clocked video signal. The flow
control on the input to this component is controlled by the
“ready” signal, which essentially pulls data out of the interface as
it is needed.
If the source is unable to provide data at a sufficient rate then
the FIFO in this component will empty. This is referred to as
underflow
. At this point the component tries to re-synchronize,
sending out blank video data and reading continuously from the
input until the start of the new frame appears, when it will re-start
the output video.
