Digital Signal Processing Reference
In-Depth Information
above. The deinterlacer, especially the motion-adaptive dein-
terlacer, requires external memory transactions because it com-
pares fields and determines if there is motion or not and that's
where the external memory transactions come into play.
In this chapter we will calculate the memory bandwidth for
a hypothetical signal chain that includes a frame buffer and
a deinterlacer
so that you can appreciate the staggering amount
of memory bandwidth required in HD video processing.
Figure 20.4
shows an example video design. We will focus on
the two deinterlacers and the two frame buffers, and for each of
these components we will calculate the worst-case memory
bandwidth.
A deinterlacer has to read four fields (or for calculation
purposes two frames) and calculate the motion value (vector) for
each pixel. This value is then compared with the previous value of
the motion vector. So it has to read in the motion vector and then
write out the final motion vector.
As shown in
Figure 20.5
, a motion-adaptive deinterlacer
requires five (master) accesses to the DDR memory:
One field write (@input rate).
Two field reads (@output rate)
e
four fields in two accesses.
e
One motion vector write.
One motion vector read.
Components that access external
memory:
2x Motion Adaptive Deinterlacer
2x Frame Buffer
All have one or more memory-mapped interfaces
Processor
System Interconnect Fabric
Deinterlacer
(MA)
Interlacer
FB
CVO
Clipper
CR
Scaler
CVI
Deinterlacer
(MA)
CR
Scaler
Interlacer
FB
CVO
CVI
Clipper
System Interconnect Fabric
High Performance DDR2 Memory Controller
Figure 20.4. An example video design.
