Digital Signal Processing Reference
In-Depth Information
Real channel at 4
Gsps
FIR
2
FIR
2
FIR
2
FIR
2
FIR
2
FIR
2
FIR
2
FIR
2
2bands of 4
6 MHz channels
=24MHz
TDMed on the
bus
Summer
Complex
Mixer
Real
Mixers
8 Channels of I&Q
at 16 Msps Time
Shared on the
same bus at 256
MHz
4 NCOs with
6 MHz channel
spacing = 24 MHz
band
Two Polyphase
NCOs: 16 Phases in
parallel
Figure 17.20. Implementation in FPGA using Altera
'
s DSPbuilder tool
ow.
The actual implementation of this design is shown in
Figure 17.20
. It is created using a toolflow known as DSPBuilder,
from FPGA manufacturer Altera. The toolflow has the capability
to automate the polyphasing, or paralleling of high data-rate
circuits with a lower FPGA clock rate, in this case, 256 MHz.
