On a direct-switched bus, the total memory bandwidth is quite small, not because of limited bus
speeds, but because each transaction occupies the bus for so long, most of the time just waiting.
Obviously, this is not an optimal situation. Sun's MBus was designed to accommodate up to four
CPUs. In practice, it was found that four CPUs generated too much bus traffic in most programs,
and the vast majority of MBus machines were shipped with just two CPUs.
Packet-Switched Buses
In a packet-switched (a.k.a. split-transaction) bus (Figure 16-3), the transaction is split between
the CPU's request and the memory's reply. The objective of this design is to overcome the
enormous periods of dead time that the direct-switched buses suffer. In this design the CPU will
release bus ownership while memory is busy looking up the address, hence freeing it for use by
other CPUs. The sequence is:
1. CPU 0 takes a cache miss. E$ must now go out to main memory to load an entire cache
line (typically, 8 words).
2. CPU 0 asserts bus ownership (perhaps waiting for a current owner to release).
3. It loads the desired address onto the bus address lines, then strobes out that address on an
address strobe line.
4. Memory sees the strobe, looks at the address, finds the proper memory bank, and then
starts looking for the data.
5. At this point, CPU 0 releases bus ownership.
6. Once found, memory reasserts bus ownership.
7. Memory then strobes the data into CPU 0's E$.
Figure 16-3. Packet-Switched Memory Bus
Total latency for a packet-switched bus is no shorter than for a direct-switched bus, but because
the bus is now free for use by other CPUs, the total throughput is much, much higher. Sun's
UE10000 can run productively with upward of 64 CPUs on a single bus.
Crossbar Switches
A crossbar is a routing switch that allows any one element on one axis to communicate directly
with any one element on the other axis. This does not affect the ability of other elements on the
first axis to communicate with other elements on the second. Contention occurs only when two
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