SEMICONDUCTOR MEMORY

In this chapter we discuss how to interface the 8031/51/52 to external memory. In Section 14.1 we study semiconductor memory concepts with emphasis on different types of ROM. In Section 14.2, address decoding concepts are discussed. In Sections 14.3 and 14.4, we explore 8031/51/52 interfacing with external ROM and RAM, respectively. We will also examine the IK-byte SRAM of the DS89C4xO chip. In Section 14.5 we will show how to access external data memory in C.
SECTION 14.1: SEMICONDUCTOR MEMORY
In this section we discuss various types of semiconductor memories and their characteristics such as capacity, organization, and access time. In the design of all microprocessor-based systems, semiconductor memories are used as primary storage for code and data. Semiconductor memories are connected directly to the CPU and they are the memory that the CPU first asks for information (code and data). For this reason, semiconductor memories are sometimes referred to as primary memory. The most widely used semiconductor memories are ROM and RAM. Before we discuss different types of RAM and ROM, we discuss some important terminology common to all semiconductor memories, such as capacity, organization, and speed.
Memory capacity
The number of bits that a semiconductor memory chip can store is called chip capacity. It can be in units of Kbits (kilobits), Mbits (megabits), and so on. This must be distinguished from the storage capacity of computer systems. While the memory capacity of a memory 1C chip is always given in bits, the memory capacity of a computer system is given in bytes. For example, an article in a technical journal may state that the 128M chip has become popular. In that case, it is understood, although it is not mentioned, that 128M means 128 megabits since the article is referring to an 1C memory chip. However, if an advertisement states that a computer comes with 128M memory, it is understood that 128M means 128 megabytes since it is referring to a computer system . .
Memory organization
Memory chips are organized into a number of locations within the 1C. Each location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is designed internally. The number of bits that each location within the memory chip can hold is always equal to the number of data pins on the chip. How many locations exist inside a memory chip? That depends on the number of address pins. The number of locations within a memory 1C always equals 2 to the power of the number of address pins. Therefore, the total number of bits that a memory chip can store is equal to the number of locations times the number of data bits per location. To summarize:
  1. A memory chip contains T locations, where x is the number of address pins.
  2. Each location contains y bits, where y is the number of data pins on the chip.

The entire chip will contain 2V x y bits, where x is the number of address pins
and y is the number of data pins on the chip.





Speed
One of the most important characteristics of a memory chip is the speed at which its data can be accessed. To access the data, the address is presented to the address pins, the READ pin is activated, and after a certain amount of time has elapsed, the data shows up’at the data pins. The shorter this elapsed time, the better, and consequently, the more expensive the memory chip. The speed of the memory chip is commonly referred to as its access time. The access time of memory chips varies from a few nanoseconds to hundreds of nanoseconds, depending on the 1C technology used in the design and fabrication process.
The three important memory characteristics of capacity, organization, and access time will be explored extensively in this chapter. Table 14-1 serves as a reference for the calculation of memory characteristics. Examples 14-1 and 14-2 demonstrate these concepts.
Example 14-1
A given memory chip has 12 address pins and 4 data pins. Find: (a) the organization, and (b) the capacity.
Solution:
  1. This memory chip has 4096 locations (212 = 4096), and each location can hold 4 bits
    of data. This gives an organization of 4096 x 4, often represented as 4Kx4.
  2. The capacity is equal to 16K bits since there is a total of 4K locations and each loca
    tion can hold 4 bits of data.
Example 14-2
A 512K memory chip has 8 pins for data. Find:
(a) the organization, and (b) the number of address pins for this memory chip.
Solution:
  1. A memory chip with 8 data pins means that each location within the chip can hold
    8 bits of data. To find the number of locations within this memory chip, divide the
    capacity by the number of data pins. 512K/8 = 64K; therefore, the organization for
    this memory chip is 64Kx8.
  1. The chip has 16 address lines since 216 = 64K.


ROM (read-only memory)
ROM is a type of memory that does not lose its contents when the power is turned off. For this reason, ROM is also called nonvolatile memory. There are different types of read-only memory, such as PROM, EPROM, EEPROM, flash EPROM, and mask ROM. Each is explained below.
PROM (programmable ROM) and OTP
PROM refers to the kind of ROM that the user can burn information into. In other words, PROM is a user-programmable memory. For every bit of the PROM, there exists a fuse. PROM is programmed by blowing the fuses. If the information burned into PROM is wrong, that PROM must be discarded since its internal fuses are blown permanently. For this reason, PROM is also referred to as OTP (one-time programmable). Programming ROM, also called burning ROM, requires special equipment called a ROM burner or ROM programmer.
EPROM (erasable programmable ROM) and UV-EPROM
EPROM was invented to allow making changes in the contents of PROM after it is burned. In EPROM, one can program the memory chip and erase it thousands of times. This is especially necessary during development of the prototype of a microprocessor-based project. A widely used EPROM is called UV-EPROM, where UV stands for ultraviolet. The only problem with UV-EPROM is that erasing its contents can take up to 20 minutes. All UV-EPROM chips have a window through which the programmer can shine ultraviolet (UV) radiation to erase its contents. For this reason, EPROM is also referred to as UV-erasable EPROM or simply UV-EPROM. Figure 14-1 shows the pins for a UV-EPROM chip.
To program a UV-EPROM chip, the following steps must be taken:
  1. Its contents must be erased. To erase a chip, remove it from its socket on the
    system board and place it in EPROM erasure equipment to expose it to UV
    radiation for 15 – 20 minutes.
  2. Program the chip. To program a UV-EPROM chip, place it in the ROM burn
    er (programmer). To burn code or data into EPROM, the ROM burner uses
    12.5 volts or higher, depending on the EPROM type. This voltage is referred
    to as VPp in the UV-EPROM data sheet.
  1. Place the chip back into its socket on the system board.
    As can be seen from the above steps, not only is there an EPROM programmer (burner), but there is also separate EPROM erasure equipment. The main problem, and indeed the major disadvantage of UV-EPROM, is that it cannot be erased and programmed while it is in the system board. To find a solution to this problem, EEPROM was invented.
Notice the patterns of the 1C numbers in Table 14-2. For example, part number 27128-25 refers to UV-EPROM that has a capacity of 128K bits and access time of 250 nanoseconds. The capacity of the memory chip is indicated in the part number and the access time is given with a zero dropped. In part numbers, C refers to CMOS technology. Notice that 27XX always refers to UV-EPROM chips. For a comprehensive list of available memory chips see JAMECO (jameco.com) or JDR (jdr.com) catalogs.


Table 14-2: Some UV-EPROM Chips


Example 14-3
For ROM chip 27128, find the number of data and address pins.
Solution:


Figure 14-1. Pin Configurations for 27xx ROM Family
The 27128 has a capacity of 128K bits. It has 16Kx8 organization (all ROMs have 8 data pins), which indicates that there are 8 pins for data and 14 pins for address (2I4=16K).


EEPROM (electrically erasable programmable ROM)
EEPROM has several advantages over EPROM, such as the fact that its method of erasure is electrical and therefore instant, as opposed to the 20-minute erasure time required for UV-EPROM. In addition, in EEPROM one can select which byte to be erased, in contrast to UV-EPROM, in which the entire contents of ROM are erased. However, the main advantage of EEPROM is that one can program and erase its contents while it is still in the system board. It does not require physical removal of the memory chip from its socket. In other words, unlike UV-EPROM, EEPROM does not require an external erasure and programming device. To utilize EEPROM fully, the designer must incorporate the circuitry to program the EEPROM into the system board . In general, the cost per bit for EEPROM is much higher than for UV-EPROM.
Table 14-3; Some EEPROM and Flash Chips


Flash memory EPROM
Since the early 1990s, flash EPROM has become a popular user-programmable memory chip, and for good reasons. First, the erasure of the entire contents takes less than a second, or one might say in a flash, hence its name, flash memory. In addition, the erasure method is electrical, and for this reason it is sometimes referred to as flash EEPROM. To avoid confusion, it is commonly called flash memory. The major difference between EEPROM and flash memory is that when flash memory’s contents are erased, the entire device is erased, in contrast to EEPROM, where one can erase a desired section or byte. Although in some flash memories recently made available the contents are divided into blocks and the erasure can be done block by block, unlike EEPROM, flash memory has no byte erasure option. Because flash memory can be programmed while it is in its socket on the system board, it is widely used to upgrade the BIOS ROM of the PC. Some designers believe that flash memory will replace the hard disk as a mass storage medium. This would increase the performance of the computer tremendously, since


flash memory is semiconductor memory with access time in the range of 100 ns compared with disk access time in the range of tens of milliseconds. For this to happen, flash memory’s program/erase cycles must become infinite, just like hard disks. Program/erase cycle refers to the number of times that a chip can be erased and programmed before it becomes unusable. At this time, the program/erase cycle is 100,000 for flash and EEPROM, 1000 for UV-EPROM, and infinite for RAM and disks.
Mask ROM
Mask ROM refers to a kind of ROM in which the contents are programmed by the 1C manufacturer. In other words, it is not a user-programmable ROM. The term mask is used in 1C fabrication. Since the process is costly, mask ROM is used when the needed volume is high (hundreds of thousands) and it is absolutely certain that the contents will not change. It is common practice to use UV-EPROM or flash for the development phase of a project, and only after the code/data have been finalized is the mask version of the product ordered. The main advantage of mask ROM is its cost, since it is significantly cheaper than other kinds of ROM, but if an error is found in the data/code, the entire batch must be thrown away. Many manufacturers of 8051 microcontrollers support the mask ROM version of the 8051. It must be noted that all ROM memories have 8 bits for data pins; therefore, the organization is x8.
RAM (random access memory)
RAM memory is called volatile memory since cutting off the power to the 1C results in the loss of data. Sometimes RAM is also referred to as RAWM (read and write memory), in contrast to ROM, which cannot be written to. There are three types of RAM: static RAM (SRAM), NV-RAM (nonvolatile RAM), and dynamic RAM (DRAM). Each is explained separately.
SRAM (static RAM)


Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in order to keep their data. This is in contrast to DRAM, discussed below. The problem with the use of flip-flops for storage cells is that each cell requires at least 6 transistors to build, and the cell holds only 1 bit of data. In recent years, the cells have been made of 4 transistors, which still is too many. The use of 4-transistor cells plus the use of CMOS technology has given birth to a high-capacity SRAM, but its capacity is far below DRAM. Table 14-4 shows some examples of SRAM. Figure 14-2 shows the pin diagram for an SRAM chip. In Figure 14-2, notice that WE is write enable, and OE is output enable, for read and write signals, respectively.














Table 14-4: Some SRAM and NV-RAM Chips


NV-RAM (nonvolatile RAM)

Whereas SRAM is volatile, there is a new type of nonvolatile RAM called NV-RAM. Like other RAMs, it allows the CPU to read and write to it, but when the power is turned off the contents are not lost. NV-RAM combines the best of RAM and ROM: the read and write ability of RAM, plus the nonvolatility of ROM. To retain its contents, every NV-RAM chip internally is made of the following components:
  1. It uses extremely power-efficient (very, very low-power consumption) SRAM
    cells built out of CMOS.
  1. It uses an internal lithium battery as a backup energy source.
    1. It uses an intelligent control circuitry. The main job of this control circuitry is
      to monitor the Vcc pin constantly to detect loss of the external power supply.
      If the power to the Vcc pin falls below out-of-tolerance conditions, the control
      circuitry switches automatically to its internal power source, the lithium bat
      tery. The internal lithium power source is used to retain the NV-RAM contents
      only when the external power source is off.
    It must be emphasized that all three of the components above are incorporated into a single 1C chip, and for this reason nonvolatile RAM is a very expensive type of RAM as far as cost per bit is concerned. Offsetting the cost, however, is the fact that it can retain its contents up to ten years after the power has been turned off and allows one to read and write in exactly the same way as SRAM. See Table 14-4 for NV-RAM parts made by Dallas Semiconductor.


Checksum byte ROM
To ensure the integrity of the ROM contents, every system must perform the checksum calculation. The process of checksum will detect any corruption of the contents of ROM. One of the causes of ROM corruption is current surge, either when the system is turned on or during operation. To ensure data integrity in ROM, the checksum process uses what is called a checksum byte. The checksum byte is an extra byte that is tagged to the end of a series of bytes of data. To calculate the checksum byte of a series of bytes of data, the following steps can be taken.
  1. Add the bytes together and drop the carries.
    1. Take the 2′s complement of the total sum, and that is the checksum byte, which
      becomes the last byte of the series.
To perform the checksum operation, add all the bytes, including the checksum byte. The result must be zero. If it is not zero, one or more bytes of data have been changed (corrupted). To clarify these important concepts, see Example 14-4.
Example 14-4
Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH, and 52H. (a) Find the checksum byte, (b) perform the checksum operation to ensure data integrity, and (c) if the second byte 62H has been changed to 22H, show how checksum detects the error.
Solution:






DRAM (dynamic RAM)
Since the early days of the computer, the need for huge, inexpensive read/write memory has been a major preoccupation of computer designers. In 1970, Intel Corporation introduced the first dynamic RAM (random access memory). Its density (capacity) was 1024 bits and it used a capacitor to store each bit. Using a capacitor to store data cuts down the number of transistors needed to build the cell; however, it requires constant refreshing due to leakage. This is in contrast to SRAM (static RAM), whose individual cells are made of flip-flops. Since each bit in SRAM uses a single flip-flop, and each flip-flop requires 6 transistors, SRAM has much larger memory cells and consequently lower density. The use of capacitors as storage cells in DRAM results in much smaller net memory cell size.
The advantages and disadvantages of DRAM memory can be summarized as follows. The major advantages are high density (capacity), cheaper cost per bit, and lower power consumption per bit. The disadvantage is that it must be refreshed periodically because the capacitor cell loses its charge; furthermore, while DRAM is being refreshed, the data cannot be accessed. This is in contrast to SRAM’s flip-flops, which retain data as long as the power is on, do not need to be refreshed, and whose contents can be accessed at any time. Since 1970, the capacity of DRAM has exploded. After the IK-bit (1024) chip came the 4K-bit in 1973, and then the 16K chip in 1976. The 1980s saw the introduction of 64K, 256K, and finally 1M and 4M memory chips. The 1990s saw 16M, 64M, 256M, and the beginning of IG-bit DRAM chips. The 2000s, 2G-bit are standard, and as the fabrication process is getting smaller, larger memory chips will be rolling off the manufacturing line. Keep in mind that when talking about 1C memory chips, the capacity is always assumed to be in bits. Therefore, a 1M chip means a 1 megabit chip and a 256K chip means a 256K-bit memory chip. However, when talking about the memory of a computer system, it is always assumed to be in bytes.
Packaging issue in DRAM
In DRAM there is a problem of packing a large number of cells into a single chip with the normal number of pins assigned to addresses. For example, a 64K-bit chip (64Kxl) must have 16 address lines and 1 data line, requiring 16 pins to send in the address if the conventional method is used. This is in addition to Vcc power, ground, and read/write control pins. Using the conventional method of data access, the large number of pins defeats the purpose of high density and small packaging, so dearly cherished by 1C designers. Therefore, to reduce the number of pins needed for addresses, multiplexing/demultiplexing is used. The method used is to split the address in half and send in each half of the address through the same pins, thereby requiring fewer address pins. Internally, the DRAM structure is divided into a square of rows and columns. The first half of the address is called the row and the second half is called the column. For example, in the case of DRAM of 64Kxl organization, the first half of the address is sent in through the 8 pins AO – A7, and by activating RAS (row address strobe), the internal latches inside DRAM grab the first half of the address. After that, the second half of the address is sent in through the same pins, and by activating CAS (column address strobe), the internal latches inside DRAM latch the second half of the address. This




results in using 8 pins for addresses plus RAS and CAS, for a total of 10 pins, instead of the 16 pins that would be required without multiplexing. To access a bit of data from DRAM, both row and column addresses must be provided. For this concept to work, there must be a 2-by-l multiplexer outside the DRAM circuitry and a demultiplexer inside every DRAM chip. Due to the complexities associated with DRAM interfacing (RAS, CAS, the need for multiplexer and refreshing circuitry), there are DRAM controllers designed to make DRAM interfacing much easier. However, many small microcontroller-based projects that do not require much RAM (usually less than 64K bytes) use SRAM of types EEPROM and NVRAM, instead of DRAM.
DRAM organization


In the discussion of ROM, we noted that all of them have 8 pins for data. This is not the case for DRAM memory chips, which can have xl, x4, x8, or x!6 organizations. See Example 14-5.
In memory chips, the data pins are also called I/O. In some DRAMs there are separate Din and Dout pins. Figure 14-3
shows a 256Kxl DRAM chip with pins AO -A8 for address, RAS and CAS, WE (write enable), and data in and data out, as well as : power and ground.
Table 14-5: Some Widely Used DRAMs


Example 14-5
Discuss the number of pins set aside for addresses in each of the following memory
chips. (a) 16Kx4 DRAM (b) 16Kx4 SRAM
Solution:
Since 2I4=16K:
  1. For DRAM we have 7 pins (AO – A6) for the address pins and 2 pins for RAS and
    CAS.
  2. For SRAM we have 14 pins for address and no pins for RAS and CAS since they
    are associated only with DRAM. In both cases we have 4 pins for the data bus.

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