Notice the following points about the program in Example 11-2. 1. We must avoid using the memory space allocated to the interrupt vector table. Therefore, we place all the initialization codes in memory starting at 30H. The LJMP instruction is the first instruction that the 8051 executes when it is powered up. LJMP redirects the controller away from the interrupt vector table.
The ISR for Timer 0 is located starting at memory location OOOBH since it is
small enough to fit the address space allocated to this interrupt.
We enabled the Timer 0 interrupt with “MOV IE, #10000010B” in MAIN.
While the PO data is brought in and issued to P1 continuously, whenever Timer
0 is rolled over, the TFO flag is raised, and the microcontroller gets out of the
“BACK” loop and goes to OOOOBH to execute the ISR associated with Timer 0.
In the ISR for Timer 0, notice that there is no need for a “CLR TFO” instruc
tion before the RETI instruction. This is because the 8051 clears the TF flag
internally upon jumping to the interrupt vector table.