SECTION 11.5: INTERRUPT PRIORITY IN THE 8051/52
The next topic that we must deal with is what happens if two interrupts are activated at the same time? Which of these two interrupts is responded to first? Interrupt priority is the main topic of discussion in this section.
Interrupt priority upon reset
When the 8051 is powered up, the priorities are assigned according to Table 11-3. From Table 11-3 we see, for example, that if external hardware interrupts 0 and 1 are activated at the same time, external interrupt 0 (INTO) is respond-
ed to first. Only after INTO has been serviced is INT1 serviced, since INT1 has the lower priority. In reality, the priority scheme in the table is nothing but an internal polling sequence in which the 8051 polls the interrupts in the sequence listed in Table 11-3, and responds accordingly.
Example 11-11
Discuss what happens if interrupts INTO, TFO, and INT1 are activated at the same time. Assume priority levels were set by the power-up reset and that the external hardware interrupts are edge-triggered.
Solution:
If these three interrupts are activated at the same time, they are latched and kept internally. Then the 8051 checks all five interrupts according to the sequence listed in Table 11-3. If any is activated, it services it in sequence. Therefore, when the above three interrupts are activated, IEO (external interrupt 0) is serviced first, then Timer 0 (TFO), and finally IE1 (external interrupt 1).
Figure 11-8. Interrupt Priority Register (Bit-addressable)
Setting interrupt priority with the IP register
We can alter the” sequence of Table 11-3 by assigning a higher priority to any one of the interrupts. This is done by programming a register called IP (interrupt priority). Figure 11-8 shows the bits of the IP register. Upon power-up reset, the IP register contains all Os, making the priority sequence based on Table 11-3. To give a higher priority to any of the interrupts, we make the corresponding bit in the IP register high. Look at Example 11-12.
Example 11-12
(a) Program the IP register to assign the highest priority to INT1 (external interrupt 1), then (b) discuss what happens if INTO, INT1, and TFO are activated at the same time. Assume that the interrupts are both edge-triggered.
Solution:
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MOV IP,#000001006 ;IP.2 = 1 to assign INT1 higher priority
The instruction “SETB IP.2″ also will do the same thing as the above line since
IP is bit-addressable.
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The instruction in Step (a) assigned a higher priority to INT1 than the others; there
fore, when INTO, INT1, and TFO interrupts are activated at the same time, the 8051
services INT1 first, then it services INTO, then TFO. This is due to the fact that INT1
has a higher priority than the other two because of the instruction in Step (a). The
instruction in Step (a) makes both the INTO and TFO bits in the IP register 0. As a
result, the sequence in Table 11 -3 is followed, which gives a higher priority to INTO
over TFO.
Example 11-13
Assume that after reset, the interrupt priority is set by the instruction “MOV IP, 400001100B”. Discuss the sequence in which the interrupts are serviced.
Solution:
The instruction “MOV IP, #0 0 0 0110 OB” (B is for binary) sets the external interrupt 1 (INT1) and Timer 1 (TF1) to a higher priority level compared with the rest of the interrupts. However, since they are polled according to Table 11-3, they will have the following priority.
Another point that needs to be clarified is the interrupt priority when two or more interrupt bits in the IP register are set to high. In this case, while these interrupts have a higher priority than others, they are serviced according to the sequence of Table 11-3. See Example 11-13.
Interrupt inside an interrupt
What happens if the 8051 is executing an ISR belonging to an interrupt and another interrupt is activated? In such cases, a high-priority interrupt can interrupt a low-priority interrupt. This is an interrupt inside an interrupt. In the 8051 a low-priority interrupt can be interrupted by a higher-priority interrupt, but not by another low-priority interrupt. Although all the interrupts are latched and kept internally, no low-priority interrupt can get the immediate attention of the CPU until the 8051 has finished servicing the high-priority interrupts.
Triggering the interrupt by software
There are times when we need to test an ISR by way of simulation. This can be done with simple instructions to set the interrupts high and thereby cause the 8051 to jump to the interrupt vector table. For example, if the IE bit for Timer 1 is set, an instruction such as “SETS TF1″ will interrupt the 8051 in whatever it is doing and force it to jump to the interrupt vector table. In other words, we do not need to wait for Timer 1 to roll over to have an interrupt. We can cause an interrupt with an instruction that raises the interrupt flag.
