The 8052 microcontroller is an enhanced version of the 8051. In recent years the 8052 has replaced the 8051 due to many of its new features. DS89C420/30 is an example of 8052 architecture. One of the new features of the 8052 is an extra 128 bytes of on-chip RAM space. In other words, the 8051 has only 128 bytes of on-chip RAM, while the 8052 has 256 bytes of it. To understand it, first let’s recall the following two facts from earlier discussion in this chapter and Chapter 2.
  1. The 8051 has 128 bytes of on-chip RAM with addresses 00 – 7FH. They are
    used for (a) register banks (addresses 00 – 1FH), (b) bit-addressable RAM
    space (addresses 20 – 2FH), and (c) the scratch pad (addresses 30 – 7FH).
  2. Another 128 bytes of on-chip RAM with addresses 80 – FFH are designated as
    Special Function Registers (SFRs). Again, the SFRs are accessed by direct
    addressing mode as we saw earlier in this chapter.
In addition to the above two features, the 8052 has another 128 bytes of on-chip RAM with addresses 80 – FFH. This extra 128 bytes of on-chip RAM is often called upper memory to distinguish it from the lower 128 bytes of 00 – 7FH. The only problem is, the address space 80 – FFH is the same address space assigned to the SFRs. In other words, they are physically two separate memories, but they have the same addresses. This parallel address space in the 8052 forces us to use two different addressing modes to access them as described next.
  1. To access the SFRs, we use direct addressing mode. The instruction “MOV
    90H, #55H” is an example of accessing the SFR with direct addressing
    mode. Since 90H is the address of PI, this is same as “MOV PI, #55H”.

To access the upper 128 bytes, we use the indirect addressing mode, which
uses RO and Rl registers as pointers. Therefore, instructions “MOV @RO , A”
and “MOV @R1, A” are employed to access the upper memory as long as reg
isters RO and Rl have values of 80H or higher. For example, the following

codes will put 55H into address 90H of the upper 128 bytes of RAM.

Figure 5-4 shows the parallel space shared between the SFR and the upper 128 bytes of RAM in the 8052. Example 5-26 shows how to access the upper 128 bytes of on-chip RAM in the 8052 microcontroller.

Figure 5-4. 8052 On-Chip RAM Address Space

Example 5-26
Write a program for the 8052 to put 55H into the upper RAM locations of 90 – 99H. Solution:

Run the above program on your simulator and examine the upper memory to see the result. (See Figures 5-5 and 5-6 for screen shots.)
Example 5-27
Assume that the on-chip ROM has a message. Write a program to copy it from code space into the upper memory space starting at address 80H. Also, as you place a byte in upper RAM, give a copy to PO.

Run the above program on your simulator and examine the upper memory to see the result.

Simulators and Data RAM space
All the major 8051/52 simulators have ways of showing the data RAM contents. Figures 5-5 and 5-6 show some of them.

Figure 5-5. Franklin Software’s Pro View Upper Memory for the 8052

Figure 5-6. Keil’s uVision Upper Memory for the 8052

This chapter described the five addressing modes of the 8051. Immediate addressing mode uses a constant for the source operand. Register addressing mode involves the use of registers to hold data to be manipulated. Direct or register indirect addressing modes can be used to access data stored in either RAM or registers of the 8051. Direct addressing mode is also used to manipulate the stack. Register indirect addressing mode uses a register as a pointer to the data. The advantage of this is that it makes addressing dynamic rather than static. Indexed addressing mode is widely used in accessing data elements of look-up table entries located in the program ROM space of the 8051.
A group of registers called the SFR (special function registers) can be accessed by their names or their addresses. We also discussed the bit-addressable ports, registers, and RAM locations and showed how to use single-bit instructions to access them directly.

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