In the first section of this appendix, we describe the instructions of the 8051 and give their formats with some examples. In many cases, more detailed programming examples will be given to clarify the instructions. These instructions will operate on any 8031, 8032, 8051, or 8052 microcontroller. The first section concludes with a list of machine cycles (clock counts) for each 8051 instruction.
In the second section, a list of all the 8051 registers is provided for ease of reference for the 8051 programmer.
SECTION A.1: THE 8051 INSTRUCTION SET
LCALL 16-bit addr also: ACALL 11-bit addr
Function: Transfers control to a subroutine
Flags: None
Flags: None
There are two types of CALLs: ACALL and LCALL. In ACALL, the target address is within 2K bytes of the current PC (program counter). To reach the target address in the 64K bytes maximum ROM space of the 8051, we must use LCALL. If calling a subroutine, the PC register (which has the address of the instruction after the ACALL) is pushed onto the stack, and the stack pointer (SP) is incremented by 2. Then the program counter is loaded with the new address and control is transferred to the subroutine. At the end of the procedure, when RET is executed, PC is popped off the stack, which returns control to the instruction after the CALL.
Notice that LCALL is a 3-byte instruction, in which one byte is the opcode, and the other two bytes are the 16-bit address of the target subroutine. ACALL is a 2-byte instruction, in which 5 bits are used for the opcode and the remaining 11 bits are used for the target subroutine address. An 11-bit address limits the range to 2K bytes.
LJMP 16-bit addr also: SJMP 8-bit addr
Function: Transfers control unconditionally to a new address.
In the 8051 there are two unconditional jumps: LJMP (long jump) and SJMP (short jump). Each is described next.
LJMP (long jump): This is a 3-byte instruction. The first byte is the opcode
and the next two bytes are the target address. As a result, LJMP is used to jump
to any address location within the 64K-byte code space of the 8051. Notice
that the difference between LJMP and LCALL is that the CALL instruction
will return and continue execution with the instruction following the CALL,
whereas JMP will not return.
SJMP (short jump): This is a 2-byte instruction. The first byte is the opcode
and the second byte is the signed number displacement, which is added to the
PC (program counter) of the instruction following the SJMP to get the target
address. Therefore, in this jump the target address must be within-128 to +127
bytes of the PC (program counter) of the instruction after the SJMP since a sin-
Notice that the MOVC instruction transfers data from the internal ROM space of the 8051 into register A. This internal ROM space belongs to program (code) on-chip ROM of the 8051. To access off-chip memory, that is, memories connected externally, we use the MOVX instruction. See MOVX for further discussion.
MOVC A,@A+PC
Function: Move code byte
Flags: None
Flags: None
This instruction moves a byte of data located in the program (code) area to A. The address of the desired byte of data is formed by adding the program counter (PC) register to the original value of the accumulator. Contrast this instruction with “MOVC A, ©A+DPTR”. Here the PC is used instead of DPTR to generate the data address.
Example: Look-up table SQUR has the squares of values between 0 and 9, and register R3 has the values of 0 to 9. Write a program to fetch the squares from the table. Use the “MOVC A, @A+PC” instruction (this is a rewrite of an example of the previous instruction “MOVC A, ©A+DPTR”).
The following should be noted concerning the above code.
The program counter, which is pointing to instruction RET, is added to regis
ter A to form the address of the desired data. In other words, the PC is incre
mented to the address of the next instruction before it is added to the original
value of the accumulator.
The role of “INC A” should be emphasized. We need instruction “INC A” to
bypass the single byte of opcode belonging to the RET instruction.
(c) This method is preferable over “MOVC A, @A+DPTR” if we do not want to
divide the program code space into two separate areas of code and data. As a
result, we do not waste valuable on-chip code space located between the last
byte of program (code) and the beginning of the data space where the look-up
table is located.
MOVX dest-byte,sou rce-byte
Function: Move external
Flags: None
Flags: None
This instruction transfers data between external memory and register A. As discussed in Chapter 14, the 8051 has 64K bytes of data space in addition to the 64K bytes of code space. This data space must be connected externally. This instruction allows us to access externally connected memeory. The address of external memory being accessed can be 16-bit or 8-bit as explained below.
(a) The 16-bit external memory address is held by the DPTR register.
MOVX A,@DPTR
This moves into the accumulator a byte from external memory whose address is pointed to by DPTR. In other words, this brings data into the CPU (register A) from the off-chip memory of the 8051.
MOVX @DPTR,A
This moves the contents of the accumulator to the external memory location whose address is held by DPTR. In other words, this takes data from inside the CPU (register A) to memory outside the 8051.
(b) The 8-bit address of external memory is held by RO or Rl.
MOVX A,@Ri /where i = 0 or 1
This moves to the accumulator a byte from external memory whose 8-bit address is pointed to by RO (or Rl in MOVX A,@R1).
MOVX @Ri,A
This moves a byte from register A to an external memory location whose 8-bit address is held by RO (or Rl in MOVX @R1,A)
The 16-bit address version of this instruction is widely used to access external memory while the 8-bit version is used to access external I/O ports.
MUL AB
Function: Multiply A x B
Flags: OV, CY
Flags: OV, CY
This multiplies an unsigned byte in A by an unsigned byte in register B. The result is placed in A and B where A has the lower byte and B has the higher byte.
Figure 14-17. 8031 Connection to External Program ROM, Data RAM, and Data ROM
Interfacing to large external memory
Figure 14-18. 8051 Accessing 256Kx8 External NV-RAM
In some applications we need a large amount (256K. bytes, for example) of memory to store data. However, the 8051 can support only 64K bytes of external data memory since DPTR is 16-bit. To solve this problem, we connect AO – A15 of the 8051 directly to the external memory’s AO – A15 pins, and use some of the PI pins to access the 64K-byte blocks inside the single 256Kx8 memory chip. This is shown in Example 14-14, and illustrated in Figure 14-18.
PUSH direct
Function: Push onto the stack
Flags: None
Flags: None
This copies the indicated byte onto the stack and increments SP by 1. Notice that this instruction supports only direct addressing mode. Therefore, instructions such as “PUSH A” or “PUSH R3″ are illegal. Instead, we must write “PUSH OEOH” where EOH is the RAM address belonging to register A and “PUSH 03″ where 03 is the RAM address of R3 of bank 0.
RET
Function: Return from subroutine
Flags: None
Flags: None
This instruction is used to return from a subroutine previously entered by instructions LCALL or ACALL. The top two bytes of the stack are popped into the program counter (PC) and program execution continues at this new address. After popping the top two bytes of the stack into the program counter, the stack pointer (SP) is decremented by 2.
RETI
Function: Return from interrupt
Flags: None
Flags: None
This is used at the end of an interrupt service routine (interrupt handler). The top two bytes of the stack are popped into the program counter and program execution continues at this new address. After popping the top two bytes of the stack into the program counter (PC), the stack pointer (SP) is decremented by 2.
Notice that while the RET instruction is used at .the end of a subroutine associated with the ACALL and LCALL instructions, 1RET must be used for the interrupt service subroutines.
RL A
Function: Rotate left the accumulator
Flags: None
Flags: None
This rotates the bits of A left. The bits rotated out of A are rotated back into A at the opposite end.
Table A-l: 8051 Instruction Set Summary
SECTION A.2: 8051 REGISTERS
Table A-2: Special Function Register (SFR) Addresses
Figure A-l. SFR RAM Address (Byte and Bit)
Figure A-2. 128 Bytes of Internal RAM
EA IE.7 Disables all interrupts. If EA = 0, no interrupt is acknowledged.
If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
IE.6 Not implemented, reserved for future use. *
ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952).
ES IE.4 Enables or disables the serial port interrupt.
ET1 IE.3 Enables or disables timer 1 overflow interrupt.
EX1 IE.2 Enables or disables external interrupt 1.
ETO IE.1 Enables or disables timer 0 overflow interrupt.
EXO IE.O Enables or disables external interrupt 0.
* User software should not write Is to reserved bits. These bits may be used in future flash microcontrollers to invoke new features
Figure A-3. IE (Interrupt Enable) Register
.
Figure A-4. Interrupt Priority Register (Bit-addressable)
Figure A-6. Bits of the PSW Register (bit-addressable)
Figure A-8. TMOD Register (not Bit-addressable)
TF1 TCON.7 Timer 1 overflow flag. Set by hardware when timer/counter 1
overflows. Cleared by hardware as the processor vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn
timer/counter 1 on/off.
TFO TCON.5 Timer 0 overflow flag. Set by hardware when timer/counter 0
overflows. Cleared by hardware as the processor vectors to the service routine.
TRO TCON.4 Timer 0 run control bit. Set/cleared by software to turn
timer/counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag. Set by CPU when the
external interrupt edge (H-to-L transition) is detected. Cleared by CPU when the interrupt is processed. Note: This flag does not latch low-level triggered interrupts.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to
specify falling edge/low-level triggered external interrupt.
IEO TCON. 1 External interrupt 0 edge flag. Set by CPU when external
interrupt (H-to-L transition) edge detected. Cleared by CPU when interrupt is processed. Note: This flag does not latch low-level triggered interrupts.
ITO TCON.O Interrupt 0 type control bit. Set/cleared by software to specify
falling edge/low-level triggered external interrupt.
Figure A-9. TCON (Timer/Counter) Register (Bit-addressable)
